Nonvolatile memory

ABSTRACT

According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2016-155105, filed Aug. 5, 2016, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a nonvolatile memory.

BACKGROUND

Currently, nonvolatile memories such as static random access memory(SRSM) and dynamic random access memory (DRAM) are mainstream as aworking memory used in various systems. However, these memories have aproblem of high power consumption.

Thus, attempts to replace the working memory used in various system andfurther, storage memories with a magnetic memory that is faster andconsumes less power have been examined. However, it is necessary toreduce a write error rate to apply magnetic memories to various systems.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a magnetic memory according to a first embodiment;

FIG. 2 is a diagram showing a relationship between V_(assist) andI_(write);

FIG. 3 is a diagram showing a relationship between V_(assist) andI_(write);

FIG. 4 is a diagram showing a relationship between V_(assist) andI_(write);

FIG. 5 is a diagram showing the start of a write operation (0-write) ina first characteristic;

FIG. 6 is a diagram showing the end of the write operation (0-write) inthe first characteristic;

FIG. 7 is a diagram showing the start of a write operation (1-write) inthe first characteristic;

FIG. 8 is a diagram showing the end of the write operation (1-write) inthe first characteristic;

FIG. 9 is a diagram showing a read operation in the firstcharacteristic;

FIG. 10 is a diagram showing the start of the write operation (0-write)in a second characteristic;

FIG. 11 is a diagram showing the end of the write operation (0-write) inthe second characteristic;

FIG. 12 is a diagram showing the start of the write operation (1-write)in the second characteristic;

FIG. 13 is a diagram showing the end of the write operation (1-write) inthe second characteristic;

FIG. 14 is a diagram showing the read operation in the secondcharacteristic;

FIG. 15 is a diagram showing a magnetic memory according to a secondembodiment;

FIG. 16 is a diagram showing a magnetic memory according to a thirdembodiment;

FIG. 17 is a diagram showing an example of a device structure of a unitcell;

FIG. 18 is a diagram showing an example of the device structure of theunit cell;

FIG. 19 is a diagram showing an example of the device structure of theunit cell;

FIG. 20 is a diagram showing an example of the device structure of amemory cell;

FIG. 21 is a diagram showing an example of the device structure of thememory cell;

FIG. 22 is a diagram showing an example of the device structure of thememory cell;

FIG. 23 is a diagram showing an example of a read/write circuit;

FIG. 24 is a diagram showing an example of a write operation (first);

FIG. 25 is a diagram showing an example of a write operation (second);

FIG. 26 is a waveform chart showing changes of main signals in a writeoperation;

FIG. 27 is a diagram showing characteristics of a magnetic memoryaccording to a fourth embodiment;

FIG. 28 is a diagram showing the start of the write operation (first);

FIG. 29 is a diagram showing the end of the write operation (first);

FIG. 30 is a diagram showing the start of the write operation (second)of a selected bit;

FIG. 31 is a diagram showing the end of the write operation (second) ofthe selected bit;

FIG. 32 is a diagram showing the start of the write operation (second)of a non-selected bit;

FIG. 33 is a diagram showing the end of the write operation (second) ofthe non-selected bit;

FIG. 34 is a diagram showing characteristics of a magnetic memoryaccording to a fifth embodiment;

FIG. 35 is a diagram showing the start of the write operation (first);

FIG. 36 is a diagram showing the end of the write operation (first);

FIG. 37 is a diagram showing the start of the write operation (second)of the selected bit;

FIG. 38 is a diagram showing the end of the write operation (second) ofthe selected bit;

FIG. 39 is a diagram showing the start of the write operation (second)of the non-selected bit;

FIG. 40 is a diagram showing the end of the write operation (second) ofthe non-selected bit; and

FIGS. 41A and 41B are signal waveform diagrams shown for explaining anexample in which a write error rate is reduced.

DETAILED DESCRIPTION

In general, according to one embodiment, a nonvolatile memory comprises:a conductive line including a first portion, a second portion and athird portion therebetween; a storage element including a first magneticlayer, a second magnetic layer and a nonmagnetic layer therebetween, andthe first magnetic layer being connected to the third portion; and acircuit flowing a write current between the first and second portions,applying a first potential to the second magnetic layer, and blockingthe write current flowing between the first and second portions afterchanging the second magnetic layer from the first potential to a secondpotential.

Hereinafter, the embodiments will be described with reference to thedrawings.

First Embodiment

FIG. 1 shows a magnetic memory according to a first embodiment.

The magnetic memory is what is called a SOT (Spin-Orbit Torque) magneticmemory.

A conductive wire 11 has a first portion E₁, a second portion E₂, and athird portion E₃ therebetween.

For example, the first and second portions E₁, E₂ correspond to two endsof the conductive wire 11 in a direction in which the conductive wire 11extends and the third portion E₃ corresponds to a center portion of theconductive wire 11.

A storage element MTJ is a 2-terminal element having a first terminaland a second terminal.

For example, the storage element MTJ is a magnetoresistive effectelement. In this case, the storage element MTJ includes a first magneticlayer (first terminal) FL having a variable magnetization direction, asecond magnetic layer (second terminal) RL having an invariablemagnetization direction, and a nonmagnetic layer (tunnel barrier layer)TN between the first and second magnetic layers FL, RL and the firstmagnetic layer FL is connected to the third portion E₃.

A first circuit 12 can generate one of a first current I_(w) _(_) _(ap)and a second current I_(w) _(_) _(p) opposite to each other between thefirst and second portions E₁, E₂.

For example, the first circuit 12 includes driver/sinkers D/S_A, D/S_Bcapable of generating one of the first current I_(w) _(_) _(ap) and thesecond current I_(w) _(_) _(p) between the first and second portions E₁,E₂ in accordance with write data (0 or 1) and a transfer gate TG.

In this case, when the write data is 1, for example, the driver/sinkerD/S_A outputs V_(dd) _(_) _(W1) (positive potential) and the driversinker D/S_B outputs a ground potential V_(ss). When a control signal φ₃becomes active (1), the transfer gate TG is turned on and a write pulseWP_A is generated. Thus, the first current I_(write) (=I_(w) _(_) _(ap))flows from the first portion E₁ toward the second portion E₂.

Also, when the write data is 0, for example, the driver/sinker D/S_Boutputs V_(dd) _(_) _(W1) (positive potential) and the driver sinkerD/S_A outputs the ground potential V_(ss). When the control signal φ₃becomes active (1), the transfer gate TG is turned on and a write pulseWP_B is generated. Thus, the second current I_(write) (=I_(w) _(_) _(p))flows from the second portion E₂ toward the first portion E₁.

In a write operation, a second circuit 13 can apply one of a firstpotential V₁ and a second potential V₂ that are difficult from eachother to the second magnetic layer (second terminal) RL of the storageelement MTJ. Also, in a read operation, the second circuit 13 can applya read potential V_(read) to the second magnetic layer (second terminal)RL of the storage element MTJ.

For example, the second circuit 13 includes a selector 14, for example,a multiplexer MUX that outputs one of the first potential V₁, the secondpotential V₂, and the read potential V_(read) based on a control signalφ₁. The potential output from the selector 14 is applied to the secondmagnetic layer (second terminal) RL of the storage element MTJ.

In this case, the control signal φ₁ is active (01) or non-active (00) ina write operation. When the control signal φ₁ is active (01), forexample, the selector 14 selects the first potential V₁. The firstpotential V₁ is, for example, a negative potential. The first potentialV₁ is different from the potential of the third portion E₃ when thefirst or second current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p))flows between the first and second portions E₁, E₂.

That is, the first potential V₁ is an assist potential V_(assist) togenerate a voltage that assists in reversing magnetization of the firstmagnetic layer FL between the second magnetic layer RL of the storageelement MTJ and the third portion E₃ of the conductive wire 11 when thefirst or second current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p))flows between the first and second portions E₁, E₂.

When the control signal φ₁ is non-active (00), for example, the selector14 selects the second potential V₂. The second potential V₂ is, forexample, the ground potential V_(ss). The second potential V₂ is apotential on standby, that is, when none of the write operation and readoperation is performed.

Also, the control signal φ₁ is active (10) or non-active (00) in a readoperation. When the control signal φ₁ is active (10), for example, theselector 14 selects the read potential V_(read). The read potentialV_(read) is, for example, a positive potential.

A controller 15 controls read operations and write operations.

In a write operation, for example, the controller 15 makes the controlsignal φ₁ active (01)/non-active (00) and applies the first potential V₁or the second potential V₂ to the second magnetic layer RL of thestorage element MTJ. Also, the controller 15 makes the control signal φ₃active/non-active and generates the first or second current I_(write)(I_(w) _(_) _(ap) or I_(w) _(_) _(p)) between the first and secondportions E₁, E₂.

In this case, the controller 15 controls the potential of the secondmagnetic layer RL of the storage element MTJ and the first or secondcurrent I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) in the orderbelow.

First, for example, the controller 15 writes first data (1) or seconddata (0) into the storage element MTJ by passing the first or secondcurrent I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) between thefirst and second portions E₁, E₂ and applying the first potential V₁ tothe second magnetic layer (second terminal) RL of the storage elementMTJ.

For example, the first data is written into the storage element MTJ whenthe first current I_(w) _(_) _(ap) is passed to between the first andsecond portions E₁, E₂ and the second data is written into the storageelement MTJ when the second current I_(w) _(_) _(ap) is passed tobetween the first and second portions E₁, E₂.

Here timing t1 when the first or second current I_(write) (I_(w) _(_)_(ap) or I_(w) _(_) _(p)) is passed to between the first and secondportions E₁, E₂ and timing t2 when the first potential V₁ is applied tothe second magnetic layer RL of the storage element MTJ may be the sameor different.

For example, as shown in FIG. 2, the timing t1 may be before the timingt2 or, as shown in FIG. 3, the timing t1 may be after the timing t2.Also, as shown in FIG. 4, the timing t1 and the timing t2 may be thesame.

Next, after writing the first data into the storage element MTJ, thecontroller 15 changes the potential of the second magnetic layer (secondterminal) RL of the storage element MTJ from the first potential V₁ tothe second potential V₂. Then, the controller 15 shuts off the first orsecond current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) betweenthe first and second portions E₁, E₂.

That is, for example, as shown in FIGS. 2 to 4, timing t3 to change thepotential of the second magnetic layer RL of the storage element MTJfrom the first potential V₁ to the second potential V₂ is before timingt4 when the first or second current I_(write) (I_(w) _(_) _(ap) or I_(w)_(_) _(p)) between the first and second portions E₁, E₂ is shut off.

In a write operation, for example, the controller 15 makes the controlsignal φ₁ active (10)/non-active (00) and applies the read potentialV_(read) to the second magnetic layer RL of the storage element MTJ. Ina read operation, a read current flows between the second magnetic layerRL of the storage element MTJ and the third portion E₃ of the conductivewire 11.

That is, the path through which the read current flows as a writecurrent is different from the path through which the first or secondcurrent I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) flows. Thus,even if the read current is set to be relatively large, a situation inwhich an erroneous write is caused by the read current can be inhibited.

To increase the effect still more, the second potential V₂ is desirablybetween the first potential V₁ and the read potential V_(read). Thiswill be described below.

In the magnetic memory in FIG. 1, the conductive wire 11 desirably has amaterial and a thickness capable of controlling the magnetizationdirection of the first magnetic layer FL of the storage element MTJ bythe spin orbit coupling or Rashba effect. For example, the conductivewire 11 contains a metal such as tantalum (Ta), tungsten (W), orplatinum (Pt) and has a thickness of 5 to 20 nm (for example, about 10nm).

In this case, if the first or second current I_(write) (I_(w) _(_) _(ap)or I_(w) _(_) _(p)) is passed to the conductive wire 11, SOT (Spin-OrbitTorque) acts on the first magnetic layer (storage layer) FL of thestorage element MTJ and thus, the magnetization direction of the firstmagnetic layer (storage layer) FL can be reversed. If, at this point,the above assist voltage is applied to the storage element MTJ, magneticcharacteristics of the first magnetic layer FL are modulated by thefield effect and the first or second current I_(write) (I_(w) _(_) _(ap)or I_(w) _(_) _(p)) needed to reverse the magnetization direction of thefirst magnetic layer FL can be made smaller.

Such a situation is shown in FIGS. 5 to 14.

That is, as shown in FIGS. 5 to 14, a first threshold line Th_p showinga boundary of whether the relation of magnetization directions of thefirst and second magnetic layers FL, RL is set to a parallel state and asecond threshold line Th_ap showing a boundary of whether the relationof magnetization directions of the first and second magnetic layers FL,RL is set to an antiparallel state have fixed inclinations in a graph inwhich a current I_(SO) flowing between the first and second portions E₁,E₂ is as the x axis and the potential V_(assist) applied to the secondmagnetic layer RL of the storage element MTJ is set as the y axis.

When, for example, as shown in FIGS. 5 to 9, a negative potential isapplied to the second magnetic layer RL of the storage element MTJ asV_(assist), the current I_(SO) needed to reverse the magnetizationdirection of the first magnetic layer FL becomes smaller, that is, afirst case (first characteristic) where the first and second thresholdlines Th_p, Th_ap are open upward is created.

Also, when, as shown in FIGS. 10 to 14, a positive potential is appliedto the second magnetic layer RL of the storage element MTJ asV_(assist), the current I_(SO) needed to reverse the magnetizationdirection of the first magnetic layer FL becomes smaller, that is, asecond case (second characteristic) where the first and second thresholdlines Th_p, Th_ap are open downward is created.

However, in the first and second cases, a point X where the currentI_(SO) flowing between the first and second portions E₁, E₂ is 0 and thepotential V_(assist) applied to the second magnetic layer RL of thestorage element MTJ is 0 is assumed to be the initial state.

Also in the present example, only a voltage assist effect caused byV_(assist) is considered and the STT (Spin Transfer torque) effectaccompanying V_(assist) is not considered. The STT effect accompanyingV_(assist) will be described below.

Also, P indicates an area in which the relation of magnetizationdirections of the first and second magnetic layers FL, RL changes to aparallel state and AP indicates an area in which the relation ofmagnetization directions of the first and second magnetic layers FL, RLchanges to an antiparallel state. P/AP indicates an area in which aparallel state is maintained when the relation of magnetizationdirections of the first and second magnetic layers FL, RL is theparallel state and an antiparallel state is maintained when the relationof magnetization directions of the first and second magnetic layers FL,RL is the antiparallel state.

The parallel state is a relation in which the magnetization directionsof the first and second magnetic layers FL, RL are mutually the samedirection and the antiparallel state is a relation in which themagnetization directions of the first and second magnetic layers FL, RLare mutually reverse directions.

Then, what can be known from the first case (FIGS. 5 to 9) is that thecurrent I_(SO) needed to reverse the magnetization direction of thefirst magnetic layer FL can be made smaller by applying a negativepotential to the second magnetic layer RL of the storage element MTJ asV_(assist).

When, for example, as shown in FIG. 5, margins Δ_(w) _(_) _(p), Δ_(w)_(_) _(ap) from the first and second threshold lines Th_p, Th_ap aresecured in consideration of thermal disturbance in a write operation,write currents I_(w) _(_) _(p), I_(w) _(_) _(ap) when V_(assist) is anegative potential are smaller than write currents I_(w) _(_) _(p)′,I_(w) _(_) _(ap)′ when V_(assist) is 0V. That is, write points W_(p),W_(ap) can be set closer to 0 than write points W_(p)′, W_(ap)′.

In this case, for example, as shown in FIG. 9, the read potentialV_(read) is desirably a potential of polarity that makes reversal of themagnetization direction of the first magnetic layer FL of the storageelement MTJ difficult in a read operation. That is, in the first case(FIGS. 5 to 9), a distance Or between a read point R and the first andsecond threshold lines Th_p, Th_ap increases in a direction in whichV_(assist) is a positive potential and thus, the read potential V_(read)is desirably a positive potential.

Therefore, the second potential (for example, the ground potentialV_(ss)) V₂ becomes a potential between the first potential (for example,a negative potential) V₁ and the read potential (for example, a positivepotential) V_(read).

However, the read potential V_(read) can be set to between the firstpotential V₁ and the second potential V₂.

Also, what can be known from the second case (FIGS. 10 to 14) is thatthe current I_(SO) needed to reverse the magnetization direction of thefirst magnetic layer FL can be made smaller by applying a positivepotential to the second magnetic layer RL of the storage element MTJ asV_(assist).

When, for example, as shown in FIG. 10, the margins Δ_(w) _(_) _(p),Δ_(w) _(_) _(ap) from the first and second threshold lines Th_p, Th_apare secured in consideration of thermal disturbance in a writeoperation, write currents I_(w) _(_) _(p), I_(w) _(_) _(ap) whenV_(assist) is a positive potential are smaller than write currents I_(w)_(_) _(p)′, I_(w) _(_) _(ap)′ when V_(assist) is 0V. That is, writepoints W_(p), W_(ap) can be set closer to 0 than write points W_(p)′,W_(ap)′.

In this case, for example, as shown in FIG. 14, the read potentialV_(read) is desirably a potential of polarity that makes reversal of themagnetization direction of the first magnetic layer FL of the storageelement MTJ difficult in a read operation. That is, in the second case(FIGS. 10 to 14), the distance Δr between the read point R and the firstand second threshold lines Th_p, Th_ap increases in a direction in whichV_(assist) is a negative potential and thus, the read potential V_(read)is desirably a negative potential.

Therefore, the second potential (for example, the ground potentialV_(ss)) V₂ becomes a potential between the first potential (for example,a positive potential) V₁ and the read potential (for example, a negativepotential) V_(read).

However, the read potential V_(read) can be set to between the firstpotential V₁ and the second potential V₂.

In the first and second cases (FIGS. 5 to 14), the first or secondcurrent I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) flows betweenthe first and second portions E₁, E₂ in a write operation. That is,while the first or second current I_(write) (I_(w) _(_) _(ap) or I_(w)_(_) _(p)) flows, the third portion E₃ has a predetermined potential(for example, a positive potential).

Therefore, in consideration of the predetermined potential generated inthe third portion E₃ while the first or second current I_(write) (I_(w)_(_) _(ap) or I_(w) _(_) _(p)) flows, the first potential V₁ is set suchthat an appropriate assist voltage is applied to the storage elementMTJ. That is, in the first case, the first potential V₁ may be, insteadof a negative potential, 0V or a positive potential. In the second case,the first potential V₁ may be, instead of a positive potential, 0V or anegative potential.

A write operation (0-write) in the first case (FIGS. 5 to 9) is startedby, as shown in FIG. 5, setting V_(assist) to the first potential V₁ andI_(SO) to the write current I_(w) _(_) _(p). The order thereof may bethat, as shown in FIG. 5, I_(SO) is set to the write current I_(w) _(_)_(p) after V_(assist) is set to the first potential V₁ (steps ST₀₁→ST₀₂)or V_(assist) is set to the first potential V₁ after I_(SO) is set tothe write current I_(w) _(_) _(p) (steps ST₀₃→ST₀₄).

The write operation (0-write) in the first case is terminated bysetting, as shown in FIG. 6, V_(assist) to the second potential V₂ andthen I_(SO) to 0 (steps ST₀₅→ST₀₆). This is because, as shown in FIG. 6,by taking the route from step ST₀₅ to step ST₀₆, the minimum marginbetween the route and the second threshold line Th_ap becomes Δ.

When, for example, the route from step ST₀₇ to step ST₀₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the second threshold line Th_ap. Therefore, when the writeoperation (0-write) is terminated, a 1-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

It is assumed here that a 0-write means a write operation that puts thestorage element MTJ into a parallel state (low-resistance state).

A write operation (1-write) in the first case (FIGS. 5 to 9) is startedby, as shown in FIG. 7, setting V_(assist) to the first potential V₁ andI_(SO) to the write current I_(w) _(_) _(ap). The order thereof may bethat, as shown in FIG. 7, I_(SO) is set to the write current I_(w) _(_)_(ap) after V_(assist) is set to the first potential V₁ (stepsST₁₁→ST₁₂) or V_(assist) is set to the first potential V₁ after I_(SO)is set to the write current I_(w) _(_) _(ap) (steps ST₁₃→ST₁₄).

The write operation (1-write) in the first case is terminated bysetting, as shown in FIG. 8, V_(assist) to the second potential V₂ andthen I_(SO) to 0 (steps ST₁₅→ST₁₆). This is because, as shown in FIG. 8,by taking the route from step ST₁₅ to step ST₁₆, the minimum marginbetween the route and the first threshold line Th_p becomes Δ.

When, for example, the route from step ST₁₇ to step ST₁₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the first threshold line Th_p. Therefore, when the writeoperation (1-write) is terminated, a 0-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

It is assumed here that a 1-write means a write operation that puts thestorage element MTJ into an antiparallel state (high-resistance state).

A read operation in the first case (FIGS. 5 to 9) is performed by, asshown in FIG. 9, setting V_(assist) to the read potential V_(read). Thewrite current I_(SO) is 0 in the read operation and thus, a 0-write or1-write is not generated. In the read operation, however, inconsideration of thermal disturbance or the like, it is desirable tomake a margin Δr between the read point R and the first and secondthreshold lines Th_p, Th_ap as large as possible.

Therefore, the read point R is desirably set in an opening direction ofthe first and second threshold lines Th_p, Th_ap, that is, in adirection in which the width of the first and second threshold linesTh_p, Th_ap broadens. In the present example, the read point R is set ina direction in which the read potential V_(read) becomes a positivepotential.

A write operation (0-write) in the second case (FIGS. 10 to 14) isstarted by, as shown in FIG. 10, setting V_(assist) to the firstpotential V₁ and I_(SO) to the write current I_(w) _(_) _(p). The orderthereof may be that, as shown in FIG. 10, I_(SO) is set to the writecurrent I_(w) _(_) _(p) after V_(assist) is set to the first potentialV₁ (steps ST₂₁→ST₂₂) or V_(assist) is set to the first potential V₁after I_(SO) is set to the write current I_(w) _(_) _(p)(stepsST₂₃→ST₂₄).

The write operation (0-write) in the second case is terminated bysetting, as shown in FIG. 11, V_(assist) to the second potential V₂ andthen I_(SO) to 0 (steps ST₂₅→ST₂₆). This is because, as shown in FIG.11, by taking the route from step ST₂₅ to step ST₂₆, the minimum marginbetween the route and the second threshold line Th_ap becomes Δ.

When, for example, the route from step ST₂₇ to step ST₂₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the second threshold line Th_ap. Therefore, when the writeoperation (0-write) is terminated, a 1-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

A write operation (1-write) in the second case (FIGS. 10 to 14) isstarted by, as shown in FIG. 12, setting V_(assist) to the firstpotential V₁ and I_(SO) to the write current I_(w) _(_) _(ap). The orderthereof may be that, as shown in FIG. 12, I_(SO) is set to the writecurrent I_(w) _(_) _(ap) after V_(assist) is set to the first potentialV₁ (steps ST₃₁→ST₃₂) or V_(assist) is set to the first potential V₁after I_(SO) is set to the write current I_(w) _(_) _(ap) (stepsST₃₃→ST₃₄).

The write operation (1-write) in the second case is terminated bysetting, as shown in FIG. 13, V_(assist) to the second potential V₂ andthen I_(SO) to 0 (steps ST₃₅→ST₃₆). This is because, as shown in FIG.13, by taking the route from step ST₃₅ to step ST₃₆, the minimum marginbetween the route and the first threshold line Th_p becomes Δ.

When, for example, the route from step ST₃₇ to step ST₃₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the first threshold line Th_p. Therefore, when the writeoperation (1-write) is terminated, a 0-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

A read operation in the second case (FIGS. 10 to 14) is performed by, asshown in FIG. 14, setting V_(assist) to the read potential V_(read). Thewrite current I_(SO) is 0 in the read operation and thus, a 0-write or1-write is not generated. In the read operation, however, inconsideration of thermal disturbance or the like, it is desirable tomake a margin Or between the read point R and the first and secondthreshold lines Th_p, Th_ap as large as possible.

Therefore, the read point R is desirably set in an opening direction ofthe first and second threshold lines Th_p, Th_ap, that is, in adirection in which the width of the first and second threshold linesTh_p, Th_ap broadens. In the present example, the read point R is set ina direction in which the read potential V_(read) becomes a negativepotential.

To further reduce the write error rate, as shown in FIG. 41A, a thirdpotential V₃ can be added during writing. At this time, the thirdpotential V₃ is a potential of polarity that makes reversal of themagnetization direction of the first magnetic layer FL of the storageelement MTJ difficult (for example, a negative potential). Thus, thewrite error rate can be reduced by increasing the resistance to thethermal agitation in comparison with the standby state and preventingback-hopping.

As shown in FIG. 41B, slope may be actively added to each of thevoltages V₁ to V₃ and the write current I_(write). In particular, whenthe temperature of the write line is increased by the write currentI_(write), the error rate can be decreased by writing data with slope.

This modification can be also applied to the following embodiments.

Second Embodiment

FIG. 15 shows a magnetic memory according to a second embodiment.

The magnetic memory is what is called a SOT magnetic memory.

A conductive wire 11 has a first portion E₁, a second portion E₂, and athird portion E₃ therebetween. For example, the first and secondportions E₁, E₂ correspond to two ends of the conductive wire 11 in adirection in which the conductive wire 11 extends and the third portionE₃ corresponds to a center portion of the conductive wire 11.

Storage elements MTJ₁, MTJ₂ are 2-terminal elements having a firstterminal and a second terminal.

For example, the storage elements MTJ₁, MTJ₂ are a magnetoresistiveeffect element. In this case, the storage elements MTJ₁, MTJ₂ include afirst magnetic layer (first terminal) FL having a variable magnetizationdirection, a second magnetic layer (second terminal) RL having aninvariable magnetization direction, and a nonmagnetic layer (tunnelbarrier layer) TN between the first and second magnetic layers FL, RLand the first magnetic layer FL is connected to the third portion E₃.

A first circuit 12 can generate one of a first current I_(w) _(_) _(ap)and a second current I_(w) _(_) _(p) opposite to each other between thefirst and second portions E₁, E₂.

For example, the first circuit 12 includes driver/sinkers D/S_A, D/S_Bcapable of generating one of the first current I_(w) _(_) _(ap) and thesecond current I_(w) _(_) _(p) between the first and second portions E₁,E₂ in accordance with write data (0 or 1) and a transfer gate TG.

In this case, when the write data is 1, for example, the driver/sinkerD/S_A outputs V_(dd) _(_) _(W1) (positive potential) and the driversinker D/S_B outputs a ground potential V_(ss). When a control signal φ₃becomes active (1), the transfer gate TG is turned on and a write pulseWP_A is generated. Thus, the first current I_(write) (=I_(w) _(_) _(ap))flows from the first portion E₁ toward the second portion E₂.

Also, when the write data is 0, for example, the driver/sinker D/S_Boutputs V_(dd) _(_) _(W1) (positive potential) and the driver sinkerD/S_A outputs the ground potential V_(ss). When the control signal φ₃becomes active (1), the transfer gate TG is turned on and a write pulseWP_B is generated. Thus, the second current I_(write) (=I_(w) _(_) _(p))flows from the second portion E₂ toward the first portion E₁.

In a write operation, second circuits 13 ₁, 13 ₂ can apply one of afirst potential V₁, a second potential V₂, and a third potential V₃ thatare difficult from each other to the second magnetic layer (secondterminal) RL of the storage elements MTJ₁, MTJ₂. Also, in a readoperation, the second circuits 13 ₁, 13 ₂ can apply a read potentialV_(read) to the second magnetic layer (second terminal) RL of thestorage element MTJ.

For example, the second circuits 13 ₁, 13 ₂ include selectors 14 ₁, 14₂, for example, multiplexers MUX that output one of the first potentialV₁, the second potential V₂, the third potential V₃, and the readpotential V_(read) based on control signals φ₁₁, φ₁₂ respectively. Thepotential output from the selectors 14 ₁, 14 ₂ is applied to the secondmagnetic layer (second terminal) RL of the storage elements MTJ₁, MTJ₂.

In this case, in a write operation, the selectors 14 ₁, 14 ₂ select thefirst potential V₁ or the third potential V₃ based on the controlsignals φ₁₁, φ₁₂ respectively. The first potential V₁ is an assistpotential that enables a write operation, for example, a negativepotential. The third potential V₃ is an inhibit potential that inhibitsa write operation, for example, a positive potential. The first andthird potentials V₁, V₃ are different from the potential of the thirdportion E₃ when a first or second current I_(write) (I_(w) _(_) _(ap) orI_(w) _(_) _(p)) flows between the first and second portions E₁, E₂.

In a read operation, the selector 14 selects the read potentialV_(read). The read potential V_(read) is, for example, a positivepotential.

The second potential V₂ is a potential selected by the selectors 14 ₁,14 ₂ on standby, that is, when none of the write operation and readoperation is performed.

A controller 15 controls read operations and write operations.

For example, a case in which the storage element MTJ₁ is selected to bewritten into and the storage element MTJ₂ is not selected to be writteninto in a write operation will be considered.

In this case, a controller 15 transfers the control signal φ₁₁ to asecond circuit 13 ₁. The selector 14 ₁ applies the second potential V₂to the second magnetic layer RL of the storage element MTJ₁ based on thecontrol signal φ₁₁. Also, the controller 15 transfers the control signalφ₁₂ to a second circuit 13 ₂. The selector 14 ₂ applies the thirdpotential V₃ to the second magnetic layer RL of the storage element MTJ₂based on the control signal φ₁₂.

Further, the controller 15 transfers the control signal φ₃ to the firstcircuit 12. The first circuit 12 generates the first or second currentI_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) between the first andsecond portions E₁, E₂ based on the control signal φ₃.

Then, the controller 15 controls the potential of the second magneticlayer RL of the storage elements MTJ₁, MTJ₂ and the first or secondcurrent I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) in the orderbelow.

The controller 15 applies the third potential V₃ to the second magneticlayer RL of the storage element MTJ₂. Then, the controller 15 passes thefirst or second current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p))to between the first and second portions E₁, E₂. Due to this order, datais inhibited from being erroneously written into the storage elementMTJ₂ not to be written into.

On the other hand, the controller 15 applies the first potential V₁ tothe second magnetic layer RL of the storage element MTJ₁. The timingwhen the first potential V₁ is applied to the second magnetic layer RLof the storage element MTJ₁ may be, as described with reference to FIGS.2 to 4, after the first or second current I_(write) (I_(w) _(_) _(ap) orI_(w) _(_) _(p)) is passed to between the first and second portions E₁,E₂ or before the first or second current I_(write) (I_(w) _(_) _(ap) orI_(w) _(_) _(p)) is passed to between the first and second portions E₁,E₂.

The timing when the first potential V₁ is applied to the second magneticlayer RL of the storage element MTJ₁ may be the same as the timing whenthe first or second current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_)_(p)) is passed to between the first and second portions E₁, E₂.

Then, the first or second current I_(write) (I_(w) _(_) _(ap) or I_(w)_(_) _(p)) flows between the first and second portions E₁, E₂ and thefirst potential V₁ is applied to the second magnetic layer RL of thestorage element MTJ₁ to write, for example, first data (1) or seconddata (0) into the storage element MTJ₁.

Next, after the first or second data is written into the storage elementMTJ₁, the controller 15 changes the potential of the second magneticlayer RL of the storage element MTJ₁ from the first potential V₁ to thesecond potential V₂. Then, the controller 15 shuts off the first orsecond current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p)) betweenthe first and second portions E₁, E₂.

That is, the timing to change the potential of the second magnetic layerRL of the storage element MTJ₁ as a write target from the firstpotential V₁ to the second potential V₂ is before the timing when thefirst or second current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p))between the first and second portions E₁, E₂ is shut off. Due to thisorder, data opposite to write data is prevented from being erroneouslystored in the storage element MTJ₁ when the write operation isterminated.

Also, after the first or second data is written into the storage elementMTJ₁, the controller 15 shuts off the first or second current I_(write)(I_(w) _(_) _(ap) or I_(w) _(_) _(p)) between the first and secondportions E₁, E₂. Then, the controller 15 changes the potential of thesecond magnetic layer RL of the storage element MTJ₂ from the thirdpotential V₃ to the second potential V₂.

That is, the timing to change the potential of the second magnetic layerRL of the storage element MTJ₂ not to be written into from the thirdpotential V₃ to the second potential V₂ is after the timing when thefirst or second current I_(write) (I_(w) _(_) _(ap) or I_(w) _(_) _(p))between the first and second portions E₁, E₂ is shut off. Due to thisorder, write data is prevented from being erroneously written into thestorage element MTJ₂ when the write operation is terminated.

The read operation is the same as in the first embodiment and thus, thedescription thereof here is omitted.

Third Embodiment

FIG. 16 shows a magnetic memory according to a third embodiment.

The magnetic memory is SOT-MRAM.

SOT-MRAM 31 includes an interface 32, an internal controller 33, amemory cell array 34, and a word line decoder/driver 35. The memory cellarray 34 includes n blocks (memory cores) BK_1 to BK_n. Where n is anatural number equal to 2 or greater.

A command CMD is transferred to the internal controller 33 via theinterface 32. The command CMD includes, for example, a read command, awrite command and the like.

When the command CMD is received, the internal controller 33 outputs,for example, control signals WE₁ to WE_(n), WE1/2, W_(sel) _(_) ₁ toW_(sel) _(_) _(n) to execute the command CMD. The meanings and roles ofthese control signals will be described below.

An address signal Addr is transferred to the internal controller 33 viathe interface 32. The address signal Addr is divided into a row addressA_(row) and column addresses A_(col) _(_) ₁ to A_(col) _(_) _(n) in theinterface 32. The row address A_(row) is transferred to the word linedecoder/driver 35. The column addresses A_(col) _(_) ₁ to A_(col) _(_)_(n) are transferred to the n blocks BK_1 to BK_n.

DA₁ to DA_(n) are read data or write data transmitted/received in a readoperation or write operation.

Each block BK_k includes a sub-array A_(sub) _(_) _(k), a read/writecircuit 36, and a column selector 37.

The column selector 37 selects one of j columns (j is a natural numberequal to 2 or greater) CoL₁ to CoL_(j) and electrically connects theselected one column CoL_(p) (p is one of 1 to j) to the read/writecircuit 36.

The sub-array A_(sub) _(_) _(k) includes, for example, a cell unitCU_(ij). The cell unit CU_(ij) includes memory cells MC₁ to MC₈ andtransistors Q_(S), Q_(W). The transistors Q_(S), Q_(W) are, for example,N-channel FET (Field effect transistor).

FIGS. 17 to 22 show examples of the cell unit CU_(ij) in FIG. 16.

A conductive wire 11 extends in a first direction. The cell unit CU_(ij)corresponds to the conductive wire 11 and includes a plurality of memorycells MC₁ to MC₈. The plurality of memory cells MC₁ to MC₈ includeseight memory cells in the present example, but the present embodiment isnot limited to such an example. For example, the plurality of memorycells MC₁ to MC₈ may include two memory cells or more.

The plurality of memory cells MC₁ to MC₈ includes storage elements MTJ₁to MTJ₈ and transistors T₁ to T₈ respectively.

The storage elements MTJ₁ to MTJ₈ are each magnetoresistive effectelements. For example, each of the storage elements MTJ₁ to MTJ₈includes a first magnetic layer (storage layer) 22 having a variablemagnetization direction, a second magnetic layer (reference layer) 23having an invariable magnetization direction, and a nonmagnetic layer(tunnel barrier layer) 24 between the first and second magnetic layers22, 23 and the first magnetic layer 22 is connected to the conductivewire 11.

In this case, the conductive wire 11 desirably has a material and athickness capable of controlling the magnetization direction of thefirst magnetic layer of the storage elements MTJ₁ to MTJ₈ by the spinorbit coupling or Rashba effect. For example, the conductive wire 11contains a metal such as tantalum (Ta), tungsten (W), or platinum (Pt)and has a thickness of 5 to 20 nm (for example, about 10 nm).

The transistors T₁ to T₈ are each, for example, N-channel FET (Fieldeffect transistor). The transistors T₁ to T₈ are desirably what iscalled vertical transistors arranged on a semiconductor substrate and inwhich a channel (current path) is in a longitudinal direction in whichthe channel intersects the surface of the semiconductor substrate.

The storage element MTJ_(d) (d is one of 1 to 8) has a first terminal(storage layer) and a second terminal (reference layer) and the firstterminal is connected to the conductive wire 11. The transistor Td has athird terminal (source/drain), a fourth terminal (source/drain), achannel (current path) between the third and fourth terminals, and acontrol electrode (gate) that controls the generation of a channel andthe third terminal is connected to the second terminal. The conductivewires WL₁ to WL₈ extend, for example, in the first direction and areconnected to control electrodes of the transistors T₁ to T₈. Conductivewires LBL₁ to LBL₈ each extend, for example, in a second directionintersecting the first direction and are connected to the fourthterminal of the transistors T₁ to T₈.

The transistor Q_(S) has a channel (current path) connected between thefirst portion E₁ of the conductive wire 11 and a conductive wire SBL anda control terminal (gate) that controls the generation of a channel. Thetransistor Q_(W) has a channel (current path) connected between thesecond portion E₂ of the conductive wire 11 and a conductive wire WBLand a control terminal (gate) that controls the generation of a channel.

A conductive wire SWL extends, for example, in the first direction andis connected to control electrodes of the transistors Q_(S), Q_(W). Theconductive wires SBL, WBL each extend, for example, in the seconddirection.

In the present example, the transistor Q_(S) is connected to the firstportion E₁ of the conductive wire 11 and the transistor Q_(W) isconnected to the second portion E₂ of the conductive wire 11, but one ofthese transistors may be omitted.

In the example of FIG. 17, the conductive wire 11 is arranged in anupper portion of a semiconductor substrate 41 and the transistors Q_(S),Q_(W) are arranged in a surface area of the semiconductor substrate 41as what is called horizontal transistor (FET). Here, the horizontaltransistor is a transistor in which a channel (current path) is in adirection along the surface of the semiconductor substrate 41.

The storage elements MTJ₁ to MTJ₈ are arranged on the conductive wire 11and the transistors T₁ to T₈ are arranged on the storage elements MTJ₁to MTJ₈. The transistors T₁ to T₈ are what is called verticaltransistors. Also, the conductive wires LBL₁ to LBL₈, SBL_(j), WBL_(j)are arranged on the transistors T₁ to T₈.

In the example of FIG. 18, the conductive wire 11 is arranged in theupper portion of the semiconductor substrate 41 and the transistorsQ_(S), Q_(W) and the storage elements MTJ₁ to MTJ₈ are arranged on theconductive wire 11. The transistors T₁ to T₈ are arranged on the storageelements MTJ₁ to MTJ₈. The transistors Q_(S), Q_(W) and the transistorsT₁ to T₈ are what is called vertical transistors.

The conductive wires LBL₁ to LBL₈ are arranged on the transistors T₁ toT₈ and the conductive wires SBL_(j), WBL_(j) are arranged on thetransistors Q_(S), Q_(W).

In the example of FIG. 19, the conductive wires LBL₁ to LBL₈, SBL_(j),WBL_(j) are arranged in the upper portion of the semiconductor substrate41. The transistors T₁ to T₈ are arranged on the conductive wires LBL₁to LBL₈ and the transistors Q_(S), Q_(W) are arranged on the conductivewires SBL_(j), WBL_(j). The storage elements MTJ₁ to MTJ₈ are arrangedon the transistors T₁ to T₈.

Also, the conductive wire 11 is arranged on the transistors T₁ to T₈ andthe transistors Q_(S), Q_(W). The transistors Q_(S), Q_(W) and thetransistors T₁ to T₈ are what is called vertical transistors.

In the examples of FIGS. 17 to 19, the first and second magnetic layers22, 23 have an easy-axis of magnetization in an in-plane direction alongthe surface of the semiconductor substrate 41 and in the seconddirection intersecting the first direction in which the conductive wire11 extends.

For example, FIG. 20 shows an example of the device structure of amemory cell MC₁ in FIGS. 17 and 19. In this example, the transistor T₁includes a semiconductor pillar (for example, a silicon pillar) 25extending in a third direction intersecting the first and seconddirections, that is, in a direction intersecting the surface of thesemiconductor substrate 41, a gate insulating layer (for example,silicon oxide) 26 covering a side surface of the semiconductor pillar25, and a conductive wire WL_(i) covering the semiconductor pillar 25and the gate insulating layer 26.

In the example of FIG. 20, the easy-axis of magnetization of the firstand second magnetic layers 22, 23 is the second direction, but may be,as shown in the example of FIG. 21, the first direction or, as shown inFIG. 22, the third direction. The storage element MTJ₁ in FIGS. 20 and21 is called an in-plane magnetization magnetoresistive effect elementand the storage element MTJ₁ in FIG. 22 is called a perpendicularmagnetization magnetoresistive effect element.

Incidentally, the memory cell MC₁ in FIG. 19 is obtained by turning thedevice structure in FIGS. 20 to 22 upside down.

The memory cell MC₁ in FIGS. 20 to 22 is characterized in that, asdescribed above, the current path of the read current I_(read) used forread operation and the current path of the write current I_(write) usedfor write operation are different.

For example, the read current I_(read) in a read operation flows fromthe conductive wire LBL₁ toward the conductive wire 11 or from theconductive wire 11 toward the conductive wire LBL₁. In a writeoperation, by contrast, the write current I_(write) flows from right toleft or from left to right inside the conductive wire 11.

If the current path of the read current I_(read) used for read operationand the current path of the write current I_(write) used for writeoperation are the same, sufficient margins have to be secured for theread current I_(read) and the write current I_(write) in considerationthermal stability to prevent a write phenomenon in a read operation fromoccurring.

However, the read current I_(read) and the write current I_(write) haveboth become sufficiently small due to increasingly finer structures ofmemory cells and the like, making it difficult to secure sufficientmargins for both.

According to SOT-MRAM in the present example, the current path of theread current I_(read) and the current path of the write currentI_(write) are different and thus, sufficient margins can be secured forboth in consideration thermal stability even if the read currentI_(read) and the write current I_(write) are both small due toincreasingly finer structures of memory cells and the like.

Also, when, as described in the first and second embodiments (FIGS. 1 to15), a 0/1 write is terminated in a write operation, a write error ratecan be reduced by bringing the assist potential V_(assist) from thefirst potential V₁ back to the second potential (initial state) V₂ andthen shutting off the write current I_(write).

FIG. 23 is a diagram showing an example of the read/write circuit inFIG. 16.

The read/write circuit 36 performs a read operation or write operationin a read operation or write operation based on an instruction from theinternal controller 33 in FIG. 15.

The read/write circuit 36 includes a read circuit and a write circuit.

Here, however, only the write circuit of the read/write circuit 36 willbe described to simplify the description. This is because, like in thefirst and second embodiments, the third embodiment is characterized bythe write operation to reduce the write error rate.

The write circuit includes ROM 45, 47, selectors (multiplexers) 46, 49,51 ₁ to 51 ₈, write drivers/sinkers D/S_A, D/S_B, a transfer gate TG, adata register 48, voltage assist drivers 50 ₁ to 50 ₈, a delay circuitD, and select transistors (for example, N channel FET) T_(S), T_(U).

The write drivers/sinkers D/S_A, D/S_B have the function of generatingone of a first current I_(w) _(_) _(ap) and a second current I_(w) _(_)_(p), which are opposite to each other, in, for example, the conductivewire 11 in FIGS. 17 to 19.

Here, the first current I_(w) _(_) _(ap) is a current to write 1 to, forexample, the storage elements MTJ₁ to MTJ₈ in FIGS. 17 to 19 by the spinorbit coupling or Rashba effect, that is, a current to set the relationof magnetization directions of the first and second magnetic layers 22,23 of the storage elements MTJ₁ to MTJ₈ in FIGS. 17 to 19 to anantiparallel state.

The second current I_(w) _(_) _(p) is a current to write 0 to, forexample, the storage elements MTJ₁ to MTJ₈ in FIGS. 17 to 19 by the spinorbit coupling or Rashba effect, that is, a current to set the relationof magnetization directions of the first and second magnetic layers 22,23 of the storage elements MTJ₁ to MTJ₈ in FIGS. 17 to 19 to a parallelstate.

The first current I_(w) _(_) _(ap) and the second current I_(w) _(_)_(p) here correspond to the first current I_(w) _(_) _(ap) and thesecond current I_(w) _(_) _(p) in the first and second embodiments(FIGS. 1 to 15).

The voltage assist drivers 50 ₁ to 50 ₈ have the function ofpermitting/inhibiting a write operation using the first current I_(w)_(_) _(ap) and the second current I_(w) _(_) _(p).

When, for example, a write operation is permitted, the voltage assistdrivers 50 ₁ to 50 ₈ selectively apply the first potential V₁ that makesit easier to perform a write operation as the assist potentialV_(assist) to, for example, the conductive wires LBL₁ to LBL₈ in FIGS.17 to 19. In this case, an assist voltage that destabilizes themagnetization direction of the first magnetic layer (storage layer) 22in FIGS. 17 to 19 is generated in the storage elements MTJ₁ to MTJ₈,which makes it easier for the magnetization direction of the firstmagnetic layer 22 to reverse.

When a write operation is inhibited, the voltage assist drivers 50 ₁ to50 ₈ selectively apply the third potential V₃ that makes it moredifficult to perform a write operation as an inhibit potentialV_(inhibit) to, for example, the conductive wires LBL₁ to LBL₈ in FIGS.17 to 19. In this case, an assist voltage that destabilizes themagnetization direction of the first magnetic layer (storage layer) 22in FIGS. 17 to 19 is not generated in the storage elements MTJ₁ to MTJ₈or an inhibit voltage that stabilizes the magnetization direction of thefirst magnetic layer 22 is generated in the storage elements MTJ₁ toMTJ₈, which makes it more difficult for the magnetization direction ofthe first magnetic layer 22 to reverse.

When a write operation is inhibited, instead of applying the inhibitpotential V_(inhibit) to the conductive wires LBL₁ to LBL₈, the voltageassist drivers 50 ₁ to 50 ₈ may put the conductive wires LBL₁ to LBL₈into an electrically floating state.

Next, an example of the write operation will be described.

Write Operation

When, for example, a write command CMD is received, the internalcontroller 33 in FIG. 16 controls a write operation. The internalcontroller 33 performs a write operation by a first write operation anda second write operation.

The first write operation is an operation to write the same data (forexample, 1) into multiple bits (for example, eight bits) as writetargets.

First, conductive wires WL₁ to WL₈, SWL are activated by the word linedecoder/driver 35 in FIG. 16.

Next, the internal controller 33 in FIG. 16 sets, for example, a controlsignal WE1/2 to 0. The control signal WE1/2 is a signal to select one ofthe first write operation and the second write operation and when, forexample, the control signal WE1/2 is 0, the first write operation isselected.

In this case, the selector 46 in the read/write circuit 36 in FIG. 23selects 1 from the ROM 45 and outputs 1 as ROM data (1). Therefore, thedriver/sinker D/S_A outputs, for example, a drive potential V_(dd) _(_)_(W1) as a write pulse signal and the driver sinker D/S_B outputs, forexample, the ground potential V_(ss).

In a write operation, the control signal φ₃ is activated (high level)and so the transfer gate TG is ON.

Therefore, the write pulse signal is applied to the conductive wire SBLvia the transfer gate TG and the ground potential V_(ss) is applied tothe conductive wire WBL via the transfer gate TG. At this point, forexample, as shown in FIG. 24, the write current (first write current)I_(write) flows from the conductive wire SBL_(j) toward the conductivewire WBL_(j), that is, from left to right inside the conductive wire 11.

In the read/write circuit 36 in FIG. 23, the selector 49 selects datastored in the ROM 47 and outputs the data as ROM data (11111111).

Therefore, all of a plurality of the voltage assist drivers 50 ₁ to 50 ₈output, for example, the assist voltage V₁ to a plurality of theconductive wires LBL₁ to LBL₈.

That is, for example, as shown in FIG. 24, the write current (firstwrite current) I_(write) flows from the conductive wire SBL toward theconductive wire WBL in a state in which the assist potential V₁ isapplied to all of the plurality of conductive wires LBL₁ to LBL₈.

As a result, in the first write operation, the same data is written intoall of the multiple bits (for example, eight bits) as write targets. Itis assumed here that 1 is written in the first write, that is, all ofthe plurality of storage elements MTJ₁ to MTJ₈ are put into anantiparallel state.

The second write operation is an operation to hold (for example, if thewrite data is 1) or change from 1 to 0 (for example, if the write datais 0) the same data (for example, 1) written into the multiple bits (forexample, eight bits) as write targets in accordance with the writ data.

First, the conductive wires WL₁ to WL₈, SWL are held in an activatedstate by the word line decoder/driver 35 in FIG. 16.

Next, the internal controller 33 in FIG. 16 sets, for example, thecontrol signal WE1/2 to 1. When, for example, the control signal WE1/2is 1, the second write operation is selected.

In this case, the selector 46 in the read/write circuit 36 in FIG. 23selects 0 from the ROM 45 and outputs 0 as ROM data (0). Therefore, thedriver/sinker D/S_B outputs, for example, the drive potential V_(dd)_(_) _(W1) as a write pulse signal and the driver sinker D/S_A outputs,for example, the ground potential V_(ss).

The write pulse signal is applied to the conductive wire WBL via thetransfer gate TG and the ground potential V_(ss) is applied to theconductive wire SBL via the transfer gate TG. At this point, forexample, as shown in FIG. 25, the write current (second write current)I_(write) flows from the conductive wire WBL toward the conductive wireSBL, that is, from right to left inside the conductive wire 11.

In the read/write circuit 36 in FIG. 23, the selector 49 selects writedata (for example, 01011100) stored in the data register 48 and outputsan inverted signal (for example, 10100011) of the write data. The writedata is stored in advance in the data register 48 before the secondwrite operation is performed.

Therefore, each of the plurality of voltage assist drivers 50 ₁ to 50 ₈outputs the first potential V₁ as the assist potential V_(assist) when,for example, the inverted signal of write data is 1 and outputs thethird potential V₃ as the inhibit potential V_(inhibit) when theinverted signal of write data is 0.

That is, when, for example, as shown in FIG. 25, the inverted signal ofwrite data is 10100011, the write current (second write current)I_(write) flows from the conductive wire WBL_(j) toward the conductivewire SBL_(j) in a state in which the first potential V₁ is applied tothe conductive wires LBL₁, LBL₃, LBL₇, LBL₈ and the third potential V₃is applied to the conductive wires LBL₂, LBL₄, LBL₅, LBL₆.

As a result, in the second write operation, data of the storage elementsMTJ₁, MTJ₃, MTJ₇, MTJ₈ of multiple bits (for example, eight bits) aswrite targets is changed from 1 to 0, that is, 0 is written thereinto.Also, data of the storage elements MTJ₂, MTJ₄, MTJ₅, MTJ₆ of multiplebits (for example, eight bits) as write targets holds 1, that is, 1 iswritten thereinto.

It is assumed here that in the second write operation, 0 is selectivelywritten into the plurality of storage elements MTJ₁ to MTJ₈, that is,the plurality of storage elements MTJ₁ to MTJ₈ is selectively changedfrom the antiparallel state to the parallel state.

FIG. 26 shows a waveform chart of main signals in the above writeoperation.

What can be known from the waveform chart is that 1 is written into allthe multiple bits (eight bits) in the write operation (first). At thispoint, the voltage assist is shut off and then the write currentI_(write) is shut off at the end of the write operation. This isintended, as described above, to prevent a 0-write from erroneouslyoccurring in the 1-write.

Also, in the write operation (second), 0 is selectively written into themultiple bits (eight bits). At this point, the voltage assist is shutoff and then the write current I_(write) is shut off from the selectedbit intended for 0-write at the end of the write operation. Accordingly,a 1-write is prevented from erroneously occurring in the 0-write.

For non-selected bits not intended for the 0-write, the voltage assistis applied and then the write current I_(write) is generated at thestart of the write operation. Also, the write current I_(write) is shutoff and then the voltage assist is shut off at the end of the writeoperation. Accordingly, a 0-write does not erroneously occur in the0-write and 1 written in the write operation (first) can be heldunchanged.

The relation (order of the application/shutoff) of the voltage assistand the write current I_(write) at the start/end of a write operation inthe 0-write of a non-selected bit will be described in detail in fourthand fifth embodiments including the reason therefor.

Therefore, the timing of the application/shutoff of the voltage assistand the write current I_(write) is different between a selected bit anda non-selected bit. The control signal φ₁, the delay circuit D, thetransistors T_(S), T_(U), and the selectors 51 ₁ to 51 ₈ in FIG. 23 areelements to implement the timing in FIG. 26.

In FIG. 23, for example, in the write operation (first), the selectors51 ₁ to 51 ₈ select S (select) through control signals φ₂₁ to φ₂₈. Inthis case, the point at which the assist potential V_(assist) changesfrom V₁ to V₂ is before the point at which the write current I_(write)is shut off.

In the write operation (second), the selectors 51 ₁ to 51 ₈ selectivelyselect S (select) or U (unselect) through the control signals φ₂₁ toφ₂₈. For example, the selectors 51 ₁ to 51 ₈ corresponding to selectedbits intended for 0-write select S (select). Also, the selectors 51 ₁ to51 ₈ corresponding to non-selected bits not intended for 0-write selectU (unselect).

In this case, for a selected bit, like in the write operation (first),the point at which the assist potential V_(assist) changes from V₁ to V₂is before the point at which the write current I_(write) is shut off.

For a non-selected bit, the point at which the assist potentialV_(assist) changes from V₂ to V₁ is before the point at which the writecurrent I_(write) is applied at the start of a write operation. Also fora non-selected bit, the point at which the assist potential V_(assist)changes from V₁ to V₂ is after the point at which the write currentI_(write) is shut off at the end of a write operation.

Fourth Embodiment

FIG. 27 shows characteristics of a magnetic memory according to a fourthembodiment.

For example, as shown in the upper diagram of FIG. 27, magnetizationreversal characteristics of a magnetic memory in consideration of theSOT effect and voltage assist effect exhibit a state in which first andsecond threshold lines Th_p, Th_ap are open upward. Also, in general,the first and second threshold lines Th_p, Th_ap are bilaterallysymmetric with respect to I_(SO)=0.

However, if an assist potential V_(assist) is applied to a secondmagnetic layer RL of a storage element, a flow of electrons in avertical direction, that is, in a direction in which the first andsecond magnetic layers FL, RL are stacked arises, in the first storagelayer FL, which causes the STT effect.

For example, if the assist potential V_(assist) becomes increasinglyhigher than the potential of a third portion E₃ of a conductive wire 11,that is, with an increasing assist potential V_(assist), the STT effectby electrons flowing from the first storage layer FL toward the secondstorage layer RL becomes conspicuous. In this case, electrons having aspin in a direction opposite to the magnetization direction of thesecond magnetic layer RL generate spin torque in the first storage layerFL and thus, the magnetization directions of the first and secondstorage layers FL, RL are more likely to be in an antiparallel state.

Therefore, as shown in the middle diagram of FIG. 27, magnetizationreversal characteristics of the magnetic memory in consideration of theSTT effect shift the first and second threshold lines Th_p, Th_ap to theleft, that is, an antiparallel state is more likely to be entered and aparallel state is less likely to be entered with an increasing potentialV_(STT) applied to the second magnetic layer RL.

Similarly, if the assist potential V_(assist) becomes increasingly lowerthan the potential of the third portion E₃ of the conductive wire 11,that is, with a decreasing assist potential V_(assist), the STT effectby electrons flowing from the second storage layer RL toward the firststorage layer FL becomes conspicuous. In this case, electrons having aspin in the same direction as the magnetization direction of the secondmagnetic layer RL generate spin torque in the first storage layer FL andthus, the magnetization directions of the first and second storagelayers FL, RL are more likely to be in a parallel state.

Therefore, as shown in the middle diagram of FIG. 27, magnetizationreversal characteristics of the magnetic memory in consideration of theSTT effect shift the first and second threshold lines Th_p, Th_ap to theright, that is, a parallel state is more likely to be entered and anantiparallel state is less likely to be entered with a decreasingpotential V_(STT) applied to the second magnetic layer RL.

From the above, as shown in the lower diagram of FIG. 27, magnetizationreversal characteristics of the magnetic memory in consideration of theSOT effect, the voltage assist effect, and the STT effect decrease theinclination of the first threshold line Th_p indicating whether to entera parallel state in a graph of I_(SO) (x axis)−V_(assist) (y axis) andincreases the inclination of the second threshold line Th_ap indicatingwhether to enter an antiparallel state.

This means that with increasing V_(assist), the first and secondmagnetic layers FL, RL are less likely to enter a parallel state. Thatis, it becomes easier to switch selected bits and non-selected bits in a0-write (write operation to put a storage element into a parallel state)using the inclination of the first threshold line Th_p. On the otherhand, it becomes more difficult to switch selected bits and non-selectedbits in a 1-write (write operation to put a storage element into anantiparallel state).

Therefore, for example, in the write operation described in the thirdembodiment, it is desirable to write 1 into all of multiple bits (eightbits) by setting the 1-write as the write operation (first). Also, bysetting the 0-write as the write operation (second), 0 can beselectively written into multiple bits (eight bits) using theinclination of the first threshold line Th_p in FIG. 27.

As a result, the write error rate is further reduced in a writeoperation of the third embodiment. To make the STT effect moreconspicuous and improve bit selectivity (make the inclination of thefirst threshold line Th_p still smaller), for example, techniques ofreducing a resistance-area product (RA) of the storage element MTJ orincreasing the spin polarization rate of the first and second magneticlayers FL, RL may be combined.

Regarding the STT effect, in contrast to the above description, aparallel state may also be likely to be entered when electrons flow fromthe first magnetic layer FL toward the second magnetic layer RL and anantiparallel state may also be likely to be entered when electrons flowfrom the second magnetic layer RL toward the first magnetic layer FL.

In such a case, the middle diagram of the FIG. 27 changes tocharacteristics in which a parallel state is more likely to be enteredwith increasing V_(STT) and an antiparallel state is more likely to beentered with decreasing V_(STT). As a result, the lower diagram of FIG.27 changes to characteristics in which the inclination of the firstthreshold line Th_p increases and the inclination of the secondthreshold line Th_ap decreases.

Therefore, in such a case, the 0-write may be set as the write operation(first) and the 1-write may be set as the write operation (second).

Which trend of the above two cases the STT effect exhibits depends on,for example, band filling of the magnetic material used for the firstmagnetic layer FL to the 3d orbit.

Next, examples of the write operation will be described.

[First Write Operation (all Bits: 1-Write)]

In the first write operation, a 1-write is performed for multiple bits(all bits).

A write operation (1-write) is started by, as shown in FIG. 28, settingV_(assist) to the first potential V₁ and I_(SO) to the write currentI_(w) _(_) _(ap). The order thereof may be that, as shown in FIG. 28,I_(SO) is set to the write current I_(w) _(_) _(ap) after V_(assist) isset to the first potential V₁ (steps ST₁₁→ST₁₂) or V_(assist) is set tothe first potential V₁ after I_(SO) is set to the write current I_(w)_(_) _(ap) (steps ST₁₃→ST₁₄).

The write operation (1-write) is terminated by setting, as shown in FIG.29, V_(assist) to the second potential V₂ and then I_(SO) to 0 (stepsST₁₅→ST₁₆).

This is because, as shown in FIG. 8, by taking the route from step ST₁₅to step ST₁₆, the minimum margin between the route and the firstthreshold line Th_p becomes Δ.

When, for example, the route from step ST₁₇ to step ST₁₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the first threshold line Th_p. Therefore, when the writeoperation (1-write) is terminated, a 0-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

[Second Write Operation: Selected Bit]

In the second write operation, a 0-write is performed for a selected bitfor which the 0-write should be performed in the order below:

A write operation (0-write) is started by, as shown in FIG. 30, settingV_(assist) to the first potential V₁ and I_(SO) to the write currentI_(w) _(_) _(p). The order thereof may be that, as shown in FIG. 30,I_(SO) is set to the write current I_(w) _(_) _(p) after V_(assist) isset to the first potential V₁ (steps ST₀₁→ST₀₂) or V_(assist) is set tothe first potential V₁ after I_(SO) is set to the write current I_(w)_(_) _(p) (steps ST₀₃→ST₀₄).

The write operation (0-write) is terminated by setting, as shown in FIG.31, V_(assist) to the second potential V₂ and then setting I_(SO) to 0(steps ST₀₅→ST₀₆). This is because, as shown in FIG. 6, by taking theroute from step ST₀₅ to step ST₀₆, the minimum margin between the routeand the second threshold line Th_ap becomes Δ.

When, for example, the route from step ST₀₇ to step ST₀₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the second threshold line Th_ap. Therefore, when the writeoperation (0-write) is terminated, a 1-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

[Second Write Operation: Non-Selected Bit]

In the second write operation, a 0-write is performed for a non-selectedbit for which the 0-write should not be performed in the order below:

A write operation (0-write) is started by, as shown in FIG. 32, settingV_(assist) to the third potential V₃ and I_(SO) to the write currentI_(w) _(_) _(p). The order thereof is that, as shown in FIG. 32,V_(assist) is set to the third potential V₃ and then I_(SO) is set tothe write current I_(w) _(_) _(p) (steps ST₂₁→ST₂₂).

A point Y is positioned inside an area P/AP and thus, a 0-write will notbe performed.

However, if I_(SO) is set to the write current I_(w) _(_) _(p) and thenV_(assist) is set to the third potential V₃, the point is close to thefirst threshold line Th_p or through a point Z beyond Th_p in a processof moving from the point X to the point Y so that a 0-write mayerroneously occur (steps ST₂₃→ST₂₄).

Therefore, when a write operation (0-write) is started, it is desirableto set V_(assist) to the third potential V₃ and then I_(SO) to the writecurrent I_(w) _(_) _(p) to reliably inhibit the occurrence of a 0-writeof the non-selected bit.

The write operation (0-write) is terminated by setting, as shown in FIG.33, I_(SO) to 0 and then V_(assist) to the second potential V₂ (stepsST₂₅→ST₂₆). This is because, as shown in FIG. 33, by taking the routefrom step ST₂₅ to step ST₂₆, the route does not cross the firstthreshold line Th_p.

In contrast, if, for example, V_(assist) is set to the second potentialV₂ and then I_(SO) is set to 0, the point is close to the firstthreshold line Th_p or through the point Z beyond Th_p in a process ofmoving from the point Y to the point X so that a 0-write erroneouslyoccurs (steps ST₂₇→ST₂₈).

Therefore, when the write operation (0-write) is terminated, it isdesirable to shut off the write current I_(w) _(_) _(p) and then setV_(assist) to the second potential V₂ to reliably inhibit the occurrenceof a 0-write of the non-selected bit.

From the above, the write error rate can be reduced without theoccurrence of an erroneous 0-write for a non-selected bit.

Fifth Embodiment

FIG. 34 shows characteristics of a magnetic memory according to a fifthembodiment.

For example, as shown in the upper diagram of FIG. 34, magnetizationreversal characteristics of a magnetic memory in consideration of theSOT effect and voltage assist effect exhibit a state in which the firstand second threshold lines Th_p, Th_ap are open downward. Also, ingeneral, the first and second threshold lines Th_p, Th_ap arebilaterally symmetric with respect to I_(SO)=0.

However, if an assist potential V_(assist) is applied to a secondmagnetic layer RL of a storage element, a flow of electrons in avertical direction, that is, in a direction in which the first andsecond magnetic layers FL, RL are stacked arises, in the first storagelayer FL, which causes the STT effect.

For example, if the assist potential V_(assist) becomes increasinglyhigher than the potential of a third portion E₃ of a conductive wire 11,that is, with an increasing assist potential V_(assist), the STT effectby electrons flowing from the first storage layer FL toward the secondstorage layer RL becomes conspicuous.

In this case, electrons having a spin in a direction opposite to themagnetization direction of the second magnetic layer RL generate spintorque in the first storage layer FL and thus, the magnetizationdirections of the first and second storage layers FL, RL are more likelyto be in an antiparallel state.

Therefore, as shown in the middle diagram of FIG. 34, magnetizationreversal characteristics of the magnetic memory in consideration of theSTT effect shift the first and second threshold lines Th_p, Th_ap to theleft, that is, an antiparallel state is more likely to be entered and aparallel state is less likely to be entered with an increasing potentialV_(STT) applied to the second magnetic layer RL.

Similarly, if the assist potential V_(assist) becomes increasingly lowerthan the potential of the third portion E₃ of the conductive wire 11,that is, with a decreasing assist potential V_(assist), the STT effectby electrons flowing from the second storage layer RL toward the firststorage layer FL becomes conspicuous. In this case, electrons having aspin in the same direction as the magnetization direction of the secondmagnetic layer RL generate spin torque in the first storage layer FL andthus, the magnetization directions of the first and second storagelayers FL, RL are more likely to be in a parallel state.

Therefore, as shown in the middle diagram of FIG. 34, magnetizationreversal characteristics of the magnetic memory in consideration of theSTT effect shift the first and second threshold lines Th_p, Th_ap to theright, that is, a parallel state is more likely to be entered and anantiparallel state is less likely to be entered with a decreasingpotential V_(STT) applied to the second magnetic layer RL.

From the above, as shown in the lower diagram of FIG. 34, magnetizationreversal characteristics of the magnetic memory in consideration of theSOT effect, the voltage assist effect, and the STT effect increase theinclination of the first threshold line Th_p indicating whether to entera parallel state in a graph of I_(SO) (x axis)−V_(assist) (y axis) anddecreases the inclination of the second threshold line Th_ap indicatingwhether to enter an antiparallel state.

This means that with decreasing V_(assist), the first and secondmagnetic layers FL, RL are less likely to enter an antiparallel state.That is, it becomes easier to switch selected bits and non-selected bitsin a 1-write (write operation to put a storage element into anantiparallel state) using the inclination of the second threshold lineTh_ap. On the other hand, it becomes more difficult to switch selectedbits and non-selected bits in a 0-write (write operation to put astorage element into a parallel state).

Therefore, for example, in the write operation described in the thirdembodiment, it is desirable to write 0 into all of multiple bits (eightbits) by setting the 0-write as the write operation (first). Also, bysetting the 1-write as the write operation (second), 1 can beselectively written into multiple bits (eight bits) using theinclination of the second threshold line Th_ap in FIG. 35.

As a result, the write error rate is further reduced in a writeoperation of the third embodiment. To make the STT effect moreconspicuous and improve bit selectivity (make the inclination of thesecond threshold line Th_ap still smaller), for example, techniques ofreducing a resistance-area product (RA) of the storage element MTJ orincreasing the spin polarization rate of the first and second magneticlayers FL, RL may be combined.

Regarding the STT effect, in contrast to the above description, aparallel state may also be likely to be entered when electrons flow fromthe first magnetic layer FL toward the second magnetic layer RL and anantiparallel state may also be likely to be entered when electrons flowfrom the second magnetic layer RL toward the first magnetic layer FL.

In such a case, the middle diagram of the FIG. 34 changes tocharacteristics in which a parallel state is more likely to be enteredwith increasing V_(STT) and an antiparallel state is more likely to beentered with decreasing V_(STT). As a result, the lower diagram of FIG.34 changes to characteristics in which the inclination of the firstthreshold line Th_p decreases and the inclination of the secondthreshold line Th_ap increases.

Therefore, in such a case, the 1-write may be set as the write operation(first) and the 0-write may be set as the write operation (second).

Which trend of the above two cases the STT effect exhibits depends on,for example, band filling of the magnetic material used for the firstmagnetic layer FL to the 3d orbit.

Next, examples of the write operation will be described.

[First Write Operation (all Bits: 0-Write)]

In the first write operation, a 0-write is performed for multiple bits(all bits).

A write operation (0-write) is started by, as shown in FIG. 35, settingV_(assist) to the first potential V₁ and I_(SO) to the write currentI_(w) _(_) _(p). The order thereof may be that, as shown in FIG. 35,I_(SO) is set to the write current I_(w) _(_) _(p) after V_(assist) isset to the first potential V₁ (steps ST₀₁→ST₀₂) or V_(assist) is set tothe first potential V₁ after I_(SO) is set to the write current I_(w)_(_) _(p) (steps ST₀₃→ST₀₄).

The write operation (0-write) is terminated by setting, as shown in FIG.36, V_(assist) to the second potential V₂ and then I_(SO) to 0 (stepsST₀₅→ST₀₆). This is because, as shown in FIG. 6, by taking the routefrom step ST₀₅ to step ST₀₆, the minimum margin between the route andthe second threshold line Th_ap becomes Δ.

When, for example, the route from step ST₀₇ to step ST₀₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the second threshold line Th_ap. Therefore, when the writeoperation (0-write) is terminated, a 1-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

[Second Write Operation: Selected Bit]

In the second write operation, a 1-write is performed for a selected bitfor which the 1-write should be performed in the order below:

A write operation (1-write) is started by, as shown in FIG. 37, settingV_(assist) to the first potential V₁ and I_(SO) to the write currentI_(w) _(_) _(ap). The order thereof may be that, as shown in FIG. 37,I_(SO) is set to the write current I_(w) _(_) _(ap) after V_(assist) isset to the first potential V₁ (steps ST₁₁→ST₁₂) or V_(assist) is set tothe first potential V₁ after I_(SO) is set to the write current I_(w)_(_) _(ap) (steps ST₁₃→ST₁₄).

The write operation (1-write) is terminated by, as shown in FIG. 38,setting V_(assist) to the second potential V₂ and then I_(SO) to 0(steps ST₁₅→ST₁₆).

This is because, as shown in FIG. 38, by taking the route from step ST₁₅to step ST₁₆, the minimum margin between the route and the firstthreshold line Th_p becomes Δ.

When, for example, the route from step ST₁₇ to step ST₁₈ is taken, theminimum margin Δ becomes larger than a minimum margin Δ′ between theroute and the first threshold line Th_p. Therefore, when the writeoperation (1-write) is terminated, a 0-write is not erroneouslygenerated due to thermal disturbance or the like so that a write errorrate can be reduced.

[Second Write Operation: Non-Selected Bit]

In the second write operation, a 1-write is performed for a non-selectedbit for which the 1-write should not be performed in the order below:

A write operation (1-write) is started by, as shown in FIG. 39, settingV_(assist) to the third potential V₃ and I_(SO) to the write currentI_(w) _(_) _(ap). The order thereof is that, as shown in FIG. 39,V_(assist) is set to the third potential V₃ and then I_(SO) is set tothe write current I_(w) _(_) _(ap) (steps ST₃₁→ST₃₂).

The point Y is positioned inside the area P/AP and thus, a 1-write willnot be performed.

However, if I_(SO) is set to the write current I_(w) _(_) _(ap) and thenV_(assist) is set to the third potential V₃, the point is close to thesecond threshold line Th_ap or through the point Z beyond Th_ap in aprocess of moving from the point X to the point Y so that a 1-write mayerroneously occur (steps ST₃₃→ST₃₄).

Therefore, when a write operation (1-write) is started, it is desirableto set V_(assist) to the third potential V₃ and then I_(SO) to the writecurrent I_(w) _(_) _(ap) to reliably inhibit the occurrence of a 1-writeof the non-selected bit.

The write operation (1-write) is terminated by, as shown in FIG. 40,setting I_(SO) to 0 and then V_(assist) to the second potential V₂(steps ST₃₅→ST₃₆). This is because, as shown in FIG. 40, by taking theroute from step ST₃₅ to step ST₃₆, the route does not cross the secondthreshold line Th_ap.

In contrast, if, for example, V_(assist) is set to the second potentialV₂ and then I_(SO) is set to 0, the point is close to the secondthreshold line Th_ap or through the point Z beyond the second thresholdline Th_ap in a process of moving from the point Y to the point X sothat a 1-write erroneously occurs (steps ST₃₇→ST₃₈).

Therefore, when the write operation (1-write) is terminated, it isdesirable to shut off the write current I_(w) _(_) _(ap) and then setV_(assist) to the second potential V₂ to reliably inhibit the occurrenceof a 1-write of the non-selected bit.

From the above, the write error rate can be reduced without theoccurrence of an erroneous 1-write for a non-selected bit.

SUMMARY

According to an embodiment, as described above, the write error rate ofa magnetic memory can be reduced.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A nonvolatile memory comprising: a conductiveline including a first portion, a second portion and a third portiontherebetween; a storage element including a first magnetic layer, asecond magnetic layer and a nonmagnetic layer therebetween, and thefirst magnetic layer being connected to the third portion; and a circuitflowing a write current between the first and second portions, applyinga first potential to the second magnetic layer, and blocking the writecurrent flowing between the first and second portions after changing thesecond magnetic layer from the first potential to a second potential. 2.The memory of claim 1, wherein the circuit writes a first data to thestorage element by flowing the write current from the first portion tothe second portion.
 3. The memory of claim 2, wherein the circuit writesa second data to the storage element by flowing the write current fromthe second portion to the first portion.
 4. The memory of claim 1,wherein the first potential is different from a potential of the thirdportion while the write current flows between the first and secondportions.
 5. The memory of claim 1, wherein polarity of the secondpotential is the opposite of polarity of the first potential.
 6. Anonvolatile memory comprising: a conductive line including a firstportion, a second portion and a third portion therebetween; a storageelement including a first terminal and a second terminal, and the firstterminal being connected to the third portion; and a circuit flowing awrite current between the first and second portions, applying a firstpotential to the second terminal, and blocking the write current flowingbetween the first and second portions after changing the second terminalfrom the first potential to a second potential.
 7. The memory of claim6, wherein the circuit writes a first data to the storage element byflowing the write current from the first portion to the second portion.8. The memory of claim 7, wherein the circuit writes a second data tothe storage element by flowing the write current from the second portionto the first portion.
 9. The memory of claim 6, wherein the firstpotential is different from a potential of the third portion while thewrite current flows between the first and second portions.
 10. Thememory of claim 6, wherein polarity of the second potential is theopposite of polarity of the first potential.
 11. A nonvolatile memorycomprising: a conductive line including a first portion, a secondportion, a third portion and a fourth portion, the third portion beingprovided between the first and second portions, and the fourth portionbeing provided between the second and third portions; a first storageelement including a first terminal and a second terminal, and the firstterminal being connected to the third portion; a second storage elementhaving a third terminal and a fourth terminal, and the third terminalbeing connected to the fourth portion; and a circuit flowing a writecurrent between the first and second portions, applying a firstpotential to the second terminal, and blocking the write current flowingbetween the first and second portions after changing the second terminalfrom the first potential to a second potential.
 12. The memory of claim11, wherein the circuit applies a third potential different from thefirst potential to the fourth terminal or sets the fourth terminal to afloating state while the write current flows between the first andsecond portions.
 13. The memory of claim 12, wherein the circuit appliesthe third potential to the fourth terminal or sets the fourth terminalto the floating state before the write current flows between the firstand second portions.
 14. The memory of claim 13, wherein the circuitchanges the fourth terminal from the third potential or the floatingstate to the second potential after the write current between the firstand second portions is blocked.
 15. The memory of claim 11, wherein thecircuit applies the first potential to the second and fourth terminalswhile the write current flows from the first portion to the secondportion.
 16. The memory of claim 15, wherein the circuit flows the writecurrent from the second portion to the first portion after flowing thewrite current from the first portion to the second portion, and appliesthe first potential to the fourth terminal while the write current flowsfrom the second portion to the first portion.
 17. The memory of claim16, wherein the circuit applies a third potential different from thefirst potential to the second terminal or sets the second terminal to afloating state while the write current flows from the second portion tothe first portion.
 18. The memory of claim 11, wherein the firstpotential is different from a potential of the third portion while thewrite current flows between the first and second portions.
 19. Thememory of claim 11, wherein polarity of the second potential is theopposite of polarity of the first potential.
 20. The memory of claim 11,wherein each of the first and second storage elements includes a firstmagnetic layer, a second magnetic layer, and a nonmagnetic layer betweenthe first and second magnetic layers, and the first magnetic layercontacts with the third portion.